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Engineer
Paradigm Works Hiring for Design Verification Engineer at Remote Full Time
Full Job Description
- As a Design Verification Engineer you will work in a SystemVerilog based UVM environment.
- You will generally create a testbench from scratch, or work from an existing testbench and make enhancements according to the design spec.
- Proper use of Assertions, and implementing functional coverage, all in a constrained random environment.
- You will work very closely with the design team.
Job Types: Full-time, Part-time, Contract, Temporary, Permanent
Pay: $125,000.00 – $230,000.00 per year
Benefits:
- 401(k)
- Dental insurance
- Flexible schedule
- Health insurance
- Paid time off
- Vision insurance
Experience level:
- 4 years
Schedule:
- Choose your own hours
- Monday to Friday
Work Location: Remote