Job Title: Sr. Front End RTL Design Engineer/ ASIC
Location: Menlo Park, CA (onsite work only)
JOB DETAIL
· More than 8+ Yrs. in the Front Design experience and methodology
· Strong knowledge in IC chip design methodology, Experience in Data path, Control Path, DMA Design and Integrations.
· Sound knowledge of RTL design and front-end design tools and flows.
· Good experience in Synthesis, Constraint Development, Linting and CDC.
· Good communication skills to work in a cross functional international team with analog, digital and software design engineers.
· The design engineer should architect digital subsystem together with system designer.
· Construction of module test cases and perform basic verification of the IP developed.
· Perform synthesis, constraints development, LINT and CDC check.
Thanks & Regards,
Prasad R | Talent Acquisition Specialist
D: 908-379-7431 | Prasad@neotechusa.com
One Cragwood Rd | South Plainfield, NJ 07080
eFax: 888-828-9871| www.neotechusa.com
Job Type: Contract
Salary: $80.00 – $85.00 per hour
Schedule:
Work Location: In person
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