Infoyogi Hiring for Debugging Engineer at San Francisco, CA Full Time

Description:

The candidate will be a member of the memory interface design team responsible for defining, specifying, and implementing future memory interface IP.

Responsibilities will include:

• Design/implement various state-of-the-art, high-speed (32+Gbps) analog/mixed-signal blocks for SerDes PHYs
• Deliver detailed specifications & documentation
• Develop initial circuit schematics and work closely with layout designers to drive designs to completion (including physical verification and backend/reliability flows)
• Drive design and layout reviews to ensure quality of deliverables and mitigate overall risk
• Work closely with various disciplines (e.g. Layout, Logical Design, Physical Design, Firmware, and Design Verification) to ensure successful cross-team engagement and high-quality execution

The successful candidate will possess:

• Solid knowledge in fundamental analog design techniques.
• Good knowledge in high-speed SerDes design (signaling/equalization techniques, analog/mixed-signalcircuit design, and signal integrity)
• Familiarity with advanced, deep submicron semiconductor technologies (experience with FinFET technology a plus)
• Solid knowledge of industry-standard tools and practices for analog/mixed-signal and high-speed digital designs (e.g., HSPICE simulator, Cadence design environment)
• Analytical thinking and inventive spirit in combination with a solid understanding of risks and risk mitigation
• Strong/effective communication skills
• Enthusiastic team-first mentality
• Experience with Unix/Linux environments

Education:

• BS + ~6 years, MS + ~4 years, or PhD + ~1-2 years with relevant experience in electrical engineering and/or computer architecture

Job Type: Contract

Salary: $50.00 – $90.00 per hour

Schedule:

• 8 hour shift

Work Location: In person

Speak with the employer
+91 09010387971