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Engineer
ARM Hiring for RTL Design Engineer Full Time
About the Role
As an RTL Design Engineer, you would be accountable for one or more functional units of the Interconnect while working closely with performance modeling, validation, and implementation teams to meet all functional requirements and performance, power, area (PPA) goals. Typical accountabilities include:
- Understanding the high-level specification and requirements of various units of Interconnect products.
- Define the Micro-architecture for an unit
- Develop Verilog RTL logic design for the unit
- Collaborate with verification team on the test plan development for the blocks and verification closure
- Debug functional or performance issues with the RTL using simulation and debug tools
- Analyze synthesis/timing s, identify and address critical areas to meet the PPA targets
What skills, experience and qualifications do I need?
- Education BS or MS in Electrical Engineering or Computer Engineering
- Prior RTL design experience is required.
- Prior verification or CAD experience is a plus
An ideal candidate will have at least 10 years of work experience in microprocessor, SoC, memory controller and interconnect IP design.
Required Experience
- CPU or compute subsystem memory micro-architecture.
- Knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE or AXI) is a plus
- Experience with Verilog or VHDL, coupled with design synthesis targeted to achieve specified frequency, power, and area targets
- Processor system knowledge including basic understanding of SoC systems as well as operating system software
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