What You’ll Do
You will participate in the ASIC design verification for Cisco high-end switching products. Author verification environment specifications, test plans, and participate in micro-architecture specification reviews.
Architect and implement complex verification environments. Define, evolve, and support the Cisco Silicon One verification methodology.
Develop and analyze functional coverage. Collaborate with the design team to analyze and close code coverage. Scope third party verification IP requirements and solicit / evaluate vendors.
Collaborate with software teams to perform HW / SW system co-simulation in advance of prototypes. Triage, debug, and root cause simulation, software bring-up, and customer issues.
Perform diagnostic and post silicon validation tests in the lab. Mentor colleagues. Responsibilities include : development of simulation models, test plan, direct and random tests, code or functional coverage, multi-chip / system simulation, and performance analysis.
Collaborate with the hardware, software designers and vendors.
Who You’ll Work With Join the Cisco Silicon One team in developing a unified silicon architecture for web scale, service provider, campus and enterprise networks.
Cisco’s RTP silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and cafe, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide.
At Cisco, we connect everything : people, processes, data, and things. We innovate everywhere, taking ambitious risks to shape the technologies that give us smart cities, connected cars, and handheld hospitals;
and we do it in style with unique personalities who aren’t afraid to change the way the world works, lives, plays and learns.
We celebrate the creativity and diversity that fuels our innovation. We are dreamers and we are doers. We Are Cisco.
You will work with outstanding talent with vast ASIC development expertise (in design, dv, dft, physical design and post silicon validation).
The team comprises of micro-architects, front-end design and verification engineers with experience ranging from 0-25 years.
we have a strong pipeline of incoming university graduates). With Cisco being a system’s company, you will also have an opportunity to work with System and Software teams that will use the ASIC and will participate in the journey of taking it from sample arrival through system validation to first customer shipments.
Who You Are You have the ability to take on problems of moderate scope involving multiple modules, work under general supervision and follow established procedures.
Your work is reviewed for soundness of technical judgment and overall adequacy and accuracy. You possess excellent written and verbal communications, team and people skills, share information and communicates clearly to team members.
You encourage and accept personal feedback, promote collaboration between team members. You also use acquired professional knowledge to make decisions, exercise judgement within defined standards and consult with management.
Minimum qualifications : Bachelor’s or Master’s degree in Electrical or Computer Engineering. 8+ years of ASIC verification experience.
Must be proficient in System Verilog / UVM. Knowledge of Linux is critical. C / C++ Must be familiar with ASIC design and verification processes, methodology and tools.
Must have strong debugging skills (post-silicon lab bring-up experience is a plus). Expertise in Verilog / System Verilog programming.
Deep understanding of object-oriented programming principles, constrained random stimulus, and a coverage driven verification approach.
Scripting experience (Python, Perl, TCL, shell programming) Strong interactive and waveform debug skills. Good written and verbal communication skills.
Collaborative and team-focused approach.
Preferred qualifications : Knowledge of Networking ASIC design verification Experience with formal verification (logic equivalency checking)
Education : MSEE / CS combined with 8+ years of related experience, or BSEE / CS combined with 8+ years of related experience.
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