Apple Hiring for Chip Level Library & Design Optimization Engineer at Cupertino, CA Full Time

Role Number:200451476

• A minimum of 10 years of experience in advanced FinFet technology development (e.g. device, integration, process, flows, EDA), circuit design, Semiconductor R&D
• Proven understanding of advanced CMOS device behavior, with practical understanding of device physics and analysis, and their impact to SoC design PPA metrics
• Thorough knowledge and understanding of yield (for a product or a technology learning vehicle), including defect pareto development and Failure Analysis methodology, Benchmarking practice
• Strong data analysis (and statistical analysis) skills; proficiency with a broad set of data analysis tools for both device and yield analysis
• Solid understanding to perform basic circuit analysis, extraction, and SPICE simulation for PPA benchmarking applications
• Great interpersonal skills to champion initiatives internally and externally, for effective communication with executive management and external partners
• Technical, analytical, and multi-functional collaboration skills

Imagine yourself at the center of shaping the forefront of advanced technology, custom IP offering that helps apple product silicon performance, power stands-out. The selected candidate will be part of a highly visible core team responsible for pathfinding and validation of standard-cell (and block-level) DTCO boosters, for better Power and Performance, in technologies with advanced transistor architecture, with the goal of co-defining / optimizing technology features & entitlements with foundry and research partners. You will have the opportunity to integrate and come-up with new insights, as well as work with a team of hardworking engineers. As an Advanced technology path-finding and design optimization engineer for the custom circuits, you will: – Be the interface to internal Technology, Logic, Memory design teams, CAD and PnR implementation team for planning production flows and with foundry on PDK requirements – To analyze and interpret the result of complex Power Performance Area (PPA) projections for logic, memory, custom IP and block level design boosters – Define strategies for IP design, considering trade offs in library architecture/design, chip level PPA requirements, technology interactions and metal stack optimizations – Collaborate with technology team and foundry to define requirements to optimize process for power, timing, area and yield for apple silicon designs

BS and a minimum of 10 years of relevant industry experience

• At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $160,700 and $282,500, and your base pay will depend on your skills, qualifications, experience, and location.

  Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.

  Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.